1. Field of the Invention
This invention relates to storage addressing and, more particularly, to apparatus and method for controlling access to the same or different pages of storage by a plurality of direct storage (memory) access (DMA) channels.
2. Discussion of the Prior Art
This invention is an improvement on that of U.S. patent application Ser. No. 231,653, now U.S. Pat. No. 4,443,847 filed Feb. 5, 1981 for PAGE ADDRESSING MECHANISM by D. J. Bradley et al, and on that of U.S. patent application Ser. No. 231,639, now U.S. Pat. No. 4,374,417 filed Feb. 5, 1981 for METHOD FOR USING PAGE ADDRESSING MECHANISM by D. J. Bradley et al, both of common assignee. Since the filing of the present application, patents have been granted for the foregoing Bradley et al. patent applications: U.S. Pat. No. 4,443,847 for application Ser. No. 231,653 and U.S. Pat. No. 4,374,417 for the application Ser. No. 231,639.
The Bradley references extend the size of memory which can be addressed by an address bus carrying N bits of information from the normal 2.sup.N locations to a multiple of 2.sup.N by providing a plurality of register means each of which is separately programmable to store data capable of being selectably provided as page signals. Selection of the page registers is made by control signals manifesting the then occurring storage operation, such as instruction fetch, storage read, or storage write operations. However, the Bradley addressing technique suffers in a system where there exists a plurality of direct storage (or memory) access channels (DMA). All DMA channels which can operate simultaneously must be directed to the same extended region of the storage address space. This may result in the necessity for double buffering of data, which reduces system performance and increases storage requirements.